Explore projects

Programming framework/library for MRA (Map-Reduce Accelerator)

Project used to teach the basics of Git and Gitlab to ACES students.

Merge multiple .cpp (class implementations) and .hpp (class declarations) files in .hpp (declarations + implementations) Split multiple .hpp (declarations + implementations) files into .cpp (class implementations) and .hpp (class declarations)

Characterize usual embedded boards (esp32 / rpi1,2,3,4 / teensy etc) regarding network data streaming (in/out) and encryption vs cpu-usage

simple test project

A board-level simulator with GUI for FPGA boards, based on Xilinx Vivado Simulator.

Pynq integration of the Gzip FPGA compressor

Java app made to automate generation of support files required by Xilins XPS, in order to easily connect a user-defined core into a Xilinx system.

Utilitary circuits for AXI4 communication - register access over AXI4-Lite, data streaming with AXI Stream, DMA over AXI4-Burst, etc