Explore projects

vLLM scheduler simulator. Simulates batched inputs and runtime performance, without running any model, based on observed runtime performance of real runs.

Universal Style Transfer using Deep Layer Aggregation

SAfety of Elderly people and Vicinity Ensuring

Programming framework/library for MRA (Map-Reduce Accelerator)

Pynq integration of the Gzip FPGA compressor

A board-level simulator with GUI for FPGA boards, based on Xilinx Vivado Simulator.

Operating Systems: Assignments: Parallel Firewall repository

Operating Systems: Assignments: Memory Allocator repository

https://open-education-hub.github.io/operating-systems/Assignments/Memory%20Allocator/