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Xilinx XPS IP core of the Xillybus DMA interface, configured with 4 FIFOs (two host to FPGA, two FPGA to host)

Utilitary circuits for AXI4 communication - register access over AXI4-Lite, data streaming with AXI Stream, DMA over AXI4-Burst, etc

Java app made to automate generation of support files required by Xilins XPS, in order to easily connect a user-defined core into a Xilinx system.

A simple generic (architecture-independent, fully inferred) asynchronous FIFO with AXI Stream interfaces