Added busy signals for DRP and PS, to ensure no operations are attempted...

Added busy signals for DRP and PS, to ensure no operations are attempted before the previous have completed; currently PS is not usable because none of the MMCM clocks use fine phase shift

hdl/vhdl/hacm.vhd

@@ -99,17 +99,19 @@ signal drp_we : std_logic;
 signal drp_en : std_logic;
 signal drp_dout : std_logic_vector(15 downto 0);
 signal drp_rdy : std_logic;
+signal drp_busy : std_logic;
 
 signal ps_en : std_logic;
 signal ps_incdec : std_logic;
 signal ps_done : std_logic;
+signal ps_busy : std_logic;
 
 begin
 
-drp_en <= (reg_wren or reg_rden) and reg_addr(7);
+drp_en <= (reg_wren or reg_rden) and reg_addr(7) and (not drp_busy);
 drp_we <= reg_wren and reg_addr(7);
 
-ps_en <= reg_wren when (reg_addr(7 downto 0) = "00001000") else '0';
+ps_en <= (reg_wren and (not ps_busy)) when (reg_addr(7 downto 0) = "00001000") else '0';
 ps_incdec <= ps_en and reg_wr_data(0);
 
 --write registers
@@ -143,13 +145,34 @@ process(reg_clk) begin
                     when "0000001" =>
                         reg_rd_data <= tsw_i & to_i & tf_i & ts_i;
                     when "0001000" =>
-                        reg_rd_data <= (1 => ps_done, others => '0');
+                        reg_rd_data <= (1 => ps_busy, others => '0');
                     when others =>
                         reg_rd_data <= (others => '0');
                 end case;
             else
 				    reg_rd_data(15 downto 0) <= drp_dout;
-                reg_rd_data(31 downto 16) <= (16 => drp_rdy, others => '0');
+                reg_rd_data(31 downto 16) <= (16 => drp_busy, others => '0');
+            end if;
+        end if;
+    end if;
+end process;
+
+-- maintain ps_busy and drp_busy
+process(reg_clk) begin
+    if(reg_clk'event and reg_clk = '1') then
+        if(rst_i = '1') then
+            ps_busy <= '0';
+            drp_busy <= '0';
+        else
+            if(ps_en = '1') then
+                ps_busy <= '1';
+            elsif(ps_done = '1') then
+               ps_busy <= '0';
+            end if;
+            if(drp_en = '1') then
+                drp_busy <= '1';
+            elsif(drp_rdy = '1') then
+                drp_busy <= '0';
             end if;
         end if;
     end if;

sim/hacm_tb.vhd

@@ -138,10 +138,13 @@ BEGIN
 
    -- Stimulus process
    stim_proc: process
-   begin		
+   begin
       reg_rden <= '0';
       reg_wren <= '0';
-
+      rst_i <= '1';
+      wait for 100 ns;
+      rst_i <= '0';
+      wait for 100 ns;
       -- write HACM CTLSTS register to reset the HACM
       wait until reg_clk'event and reg_clk = '1';
       reg_rden <= '0';
@@ -251,7 +254,31 @@ BEGIN
       wait until reg_clk'event and reg_clk = '1';
       reg_rden <= '0';
       reg_wren <= '0';
-      
+
+      -- wait for MMCM to re-lock
+      wait until lock_o = '1';
+      wait for 100 ns;
+
+      -- write HACM PSCTL register to do phase shift (increment)
+      wait until reg_clk'event and reg_clk = '1';
+      reg_rden <= '0';
+      reg_wren <= '1';
+      reg_wr_data <= x"00000001";
+      reg_addr(7 downto 0) <= "00001000";
+      wait until reg_clk'event and reg_clk = '1';
+      reg_rden <= '0';
+      reg_wren <= '0';
+
+      wait for 100 ns;
+
+      wait until reg_clk'event and reg_clk = '1';
+      reg_rden <= '0';
+      reg_wren <= '1';
+      reg_wr_data <= x"00000001";
+      reg_addr(7 downto 0) <= "00001000";
+      wait until reg_clk'event and reg_clk = '1';
+      reg_rden <= '0';
+      reg_wren <= '0';
 
 
       wait for 20 us;