Merge branch 'master' of zeus.arh.pub.ro:research/vasile

rtl/hacm.vhd

+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hacm is
+    port 
+    (
+        clk_i     : in  std_logic;
+        rst_i     : in  std_logic;
+        
+        --the following inputs are synchronous to clk_o
+        f_or_s_i  : in  std_logic;
+        ts_i      : in  std_logic_vector(7 downto 0);
+        tf_i      : in  std_logic_vector(7 downto 0);
+        to_i      : in  std_logic_vector(7 downto 0);
+        tsw_i     : in  std_logic_vector(7 downto 0);       
+
+        lock_o    : out std_logic;                  
+        clk_o     : out std_logic
+    );
+
+end hacm;
+
+architecture Behavioral of hacm is
+
+component hacm_control
+    port 
+    (
+        clk_i       : in  std_logic;
+        rst_i     : in  std_logic;
+        
+        f_or_s_i  : in  std_logic;
+        ts_i      : in  std_logic_vector(7 downto 0);
+        tf_i      : in  std_logic_vector(7 downto 0);
+        to_i      : in  std_logic_vector(7 downto 0);
+        tsw_i     : in  std_logic_vector(7 downto 0);       
+        
+        mode_o    : out std_logic;
+        stretch_o : out std_logic_vector(1 downto 0);   
+        sel_o     : out std_logic
+    );
+end component;
+
+component hacm_core
+    port 
+    (
+        clk_i       : in  std_logic;
+        mode_i    : in  std_logic; --0=CS; 1=CM
+        stretch_i : in  std_logic_vector(1 downto 0);   
+        sel_i     : in  std_logic; --0=PC; 1=CO
+        lock_o    : out std_logic;                  
+        clk_o     : out std_logic
+    );
+end component;
+
+signal hacm_mode : std_logic;
+signal hacm_stretch : std_logic_vector(1 downto 0);
+signal hacm_sel : std_logic;
+
+signal clk_internal : std_logic;
+
+begin
+
+control: hacm_control port map(
+    clk_i => clk_internal,
+    rst_i => rst_i,
+    f_or_s_i => f_or_s_i,
+    ts_i => ts_i,
+    tf_i => tf_i,
+    to_i => to_i,
+    tsw_i => tsw_i,
+    
+    mode_o => hacm_mode,
+    stretch_o => hacm_stretch,
+    sel_o => hacm_sel
+);
+
+core: hacm_core port map(
+    clk_i => clk_i,
+    mode_i => hacm_mode,
+    stretch_i => hacm_stretch,
+    sel_i => hacm_sel,
+    lock_o => lock_o,
+    clk_o => clk_internal
+);
+
+clk_o <= clk_internal;
+
+end Behavioral;
+

rtl/hacm_control.vhd

@@ -14,17 +14,20 @@ library unisim;
 use unisim.vcomponents.all;
 
 -- ENTITY ---------------------------------------------------------------------
+-- the HACM control unit receives timing and instruction info and
+-- decides which ACM strategy to utilize (stretching or multiplexing)
 entity hacm_control is
 	port 
 	(
 		clk_i	    : in  std_logic;
 		rst_i     : in  std_logic;
 		
-		f_or_s_i  : in  std_logic;
-		ts_i      : in  std_logic_vector(7 downto 0);
-		tf_i      : in  std_logic_vector(7 downto 0);
-		to_i      : in  std_logic_vector(7 downto 0);
-		tsw_i     : in  std_logic_vector(7 downto 0);		
+        --fixed-point, 5.3 format, value in nanoseconds
+		f_or_s_i  : in  std_logic;                     --indicates fast or slow instructions (1=slow, 0=fast)
+		ts_i      : in  std_logic_vector(7 downto 0);  --period of slow clock (desired)
+		tf_i      : in  std_logic_vector(7 downto 0);  --period of fast clock
+		to_i      : in  std_logic_vector(7 downto 0);  --period of slow clock (attainable)
+		tsw_i     : in  std_logic_vector(7 downto 0);  --duration of a clock switch
 		
 		mode_o    : out std_logic;
 		stretch_o : out std_logic_vector(1 downto 0);	
@@ -55,12 +58,25 @@ architecture rtl of hacm_control is
   
 begin
 
+
+--f_or_s shift register
+  process(clk_i)
+  begin
+    if(clk_i'event and clk_i = '1') then
+        sh_reg_s(99 downto 1) <= sh_reg_s(98 downto 0);
+        if(rst_i = '1') then
+            sh_reg_s(0) <= '0';
+        else
+            sh_reg_s(0) <= f_or_s_i;
+        end if;
+    end if;
+  end process;
+
 --CM/CS Decision
   process(clk_i)
   begin
     if(clk_i'event and clk_i = '1') then 	 
       if(rst_i = '1') then 
- 	     --sh_reg_s  <= (others => '0');
 		  nsi_reg_s <= (others => '0');
 		  nfi_reg_s <= "1100011";
 		  ncs_reg_s <= (others => '0');
@@ -75,7 +91,6 @@ begin
 	     tcs    <= (others => '0');
 	     mode_reg_s <= '0';
       else
-		  sh_reg_s  <= sh_reg_s(98 downto 0) & f_or_s_i;
         nsi_reg_s <= nsi_reg_s + (f_or_s_i & nand_reduce(nsi_reg_s)) - (sh_reg_s(99) & or_reduce(nsi_reg_s)); 
 		  nfi_reg_s <= nfi_reg_s + (not(f_or_s_i) & nand_reduce(nfi_reg_s)) - (not(sh_reg_s(99)) & or_reduce(nfi_reg_s));  
 		  ncs_reg_s <= ncs_reg_s + (f_or_s_i xor sh_reg_s(0)) - (sh_reg_s(99) xor sh_reg_s(98));
@@ -96,8 +111,8 @@ begin
   mode_o <= mode_reg_s;
   
 --CS/CM MUX CTRL
-  stretch_o <= "01";
-  sel_o     <= '0';
+  stretch_o <= "01" when f_or_s_i = '1' else "00";
+  sel_o     <= f_or_s_i;
 
 -------------------------------------------------------------------------------
 end rtl;
\ No newline at end of file

rtl/hacm_core.vhd

@@ -133,26 +133,26 @@ begin
     COMPENSATION         => "ZHOLD",
     STARTUP_WAIT         => FALSE,
     DIVCLK_DIVIDE        => 1,	 
-    CLKFBOUT_MULT_F      => 11.000,
+    CLKFBOUT_MULT_F      => 10.000,
     CLKFBOUT_PHASE       => 0.000,
     CLKFBOUT_USE_FINE_PS => FALSE,	 
-    CLKOUT0_DIVIDE_F     => 11.000,
+    CLKOUT0_DIVIDE_F     => 10.000,
     CLKOUT0_PHASE        => 0.000,
     CLKOUT0_DUTY_CYCLE   => 0.500,
     CLKOUT0_USE_FINE_PS  => FALSE,
-    CLKOUT1_DIVIDE       => 11,
+    CLKOUT1_DIVIDE       => 10,
     CLKOUT1_PHASE        => 90.000,
     CLKOUT1_DUTY_CYCLE   => 0.500,
     CLKOUT1_USE_FINE_PS  => FALSE,
-    CLKOUT2_DIVIDE       => 11,
+    CLKOUT2_DIVIDE       => 10,
     CLKOUT2_PHASE        => 180.000,
     CLKOUT2_DUTY_CYCLE   => 0.500,
     CLKOUT2_USE_FINE_PS  => FALSE,
-    CLKOUT3_DIVIDE       => 11,
+    CLKOUT3_DIVIDE       => 10,
     CLKOUT3_PHASE        => 270.000,
     CLKOUT3_DUTY_CYCLE   => 0.500,
     CLKOUT3_USE_FINE_PS  => FALSE,
-	 CLKOUT4_DIVIDE       => 10,
+	CLKOUT4_DIVIDE       => 11,
     CLKOUT4_PHASE        => 0.000,
     CLKOUT4_DUTY_CYCLE   => 0.500,
     CLKOUT4_USE_FINE_PS  => FALSE,

sim/hacm_tb.vhd

+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   15:56:40 03/02/2015
+-- Design Name:   
+-- Module Name:   /home/lpetrica/Documents/git/vasile/rtl/hacm/hacm_tb.vhd
+-- Project Name:  hacm
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: hacm
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY hacm_tb IS
+END hacm_tb;
+ 
+ARCHITECTURE behavior OF hacm_tb IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT hacm
+    PORT(
+         clk_i : IN  std_logic;
+         rst_i : IN  std_logic;
+         f_or_s_i : IN  std_logic;
+         ts_i : IN  std_logic_vector(7 downto 0);
+         tf_i : IN  std_logic_vector(7 downto 0);
+         to_i : IN  std_logic_vector(7 downto 0);
+         tsw_i : IN  std_logic_vector(7 downto 0);
+         lock_o : OUT  std_logic;
+         clk_o : OUT  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk_i : std_logic := '0';
+   signal rst_i : std_logic := '1';
+   signal f_or_s_i : std_logic := '0';
+   signal ts_i : std_logic_vector(7 downto 0) := "01011000";--11.0ns
+   signal tf_i : std_logic_vector(7 downto 0) := "01010000";--10.0ns
+   signal to_i : std_logic_vector(7 downto 0) := "01100100";--12.5ns
+   signal tsw_i : std_logic_vector(7 downto 0) := "01110000";--14.0ns
+
+   signal alternate_period : integer := 10;
+   signal alternate_counter : integer := 0;
+
+ 	--Outputs
+   signal lock_o : std_logic;
+   signal clk_o : std_logic;
+
+   -- Clock period definitions
+   constant clk_i_period : time := 10 ns;
+   constant clk_o_period : time := 10 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: hacm PORT MAP (
+          clk_i => clk_i,
+          rst_i => rst_i,
+          f_or_s_i => f_or_s_i,
+          ts_i => ts_i,
+          tf_i => tf_i,
+          to_i => to_i,
+          tsw_i => tsw_i,
+          lock_o => lock_o,
+          clk_o => clk_o
+        );
+
+   -- Clock process definitions
+   clk_i_process :process
+   begin
+		clk_i <= '0';
+		wait for clk_i_period/2;
+		clk_i <= '1';
+		wait for clk_i_period/2;
+   end process;
+
+   process(clk_o)
+   begin
+    if(clk_o'event and clk_o = '1') then
+        if(alternate_counter = alternate_period) then
+            f_or_s_i <= '1';
+            alternate_counter <= 0;
+        else
+            f_or_s_i <= '0';
+            alternate_counter <= alternate_counter + 1;
+        end if;
+    end if;
+   end process;
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state until after MMCM locks.
+      wait until lock_o = '1';	
+      wait for clk_i_period*200;
+      rst_i <= '0';
+      -- insert stimulus here 
+      wait for 20 us;
+      alternate_period <= 9;
+      wait for 20 us;
+      alternate_period <= 8;
+      wait for 20 us;
+      alternate_period <= 7;
+      wait for 20 us;
+      alternate_period <= 6;
+      wait for 20 us;
+      alternate_period <= 5;
+      wait for 20 us;
+      alternate_period <= 4;
+      wait for 20 us;
+      alternate_period <= 3;
+      wait for 20 us;
+      alternate_period <= 2;
+      wait for 20 us;
+      alternate_period <= 1;
+      wait;
+   end process;
+
+END;