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Smaranda ANDRONICrequested to merge
etti/dcae-public/arh/teaching/aces/2025-2026/functional-verification/project-functional-verification:main into main

Task 1

  • generate the RTL source for my IP
  • populate the interface (my_if.sv) with the signals needed for your module
  • instantiate the DUT in the top module (top.sv), connect the interface signals, generate the clock and the initial reset
  • run a simulation

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