Utils

Utilitary circuits for AXI4 communication - register access over AXI4-Lite, data streaming with AXI Stream, DMA over AXI4-Burst, etc

A simple generic (architecture-independent, fully inferred) asynchronous FIFO with AXI Stream interfaces

Merge multiple .cpp (class implementations) and .hpp (class declarations) files in .hpp (declarations + implementations) Split multiple .hpp (declarations + implementations) files into .cpp (class implementations) and .hpp (class declarations)

A generic C implementation of a hashmap using macros

Java app made to automate generation of support files required by Xilins XPS, in order to easily connect a user-defined core into a Xilinx system.

Xilinx XPS IP core of the Xillybus DMA interface, configured with 4 FIFOs (two host to FPGA, two FPGA to host)